In order to improve a carrier mobility of a field effect transistor (FET) having a hetero junction of Si and SiGe in the channel region, there is known the technique that an n-channel FET uses as a channel an Si layer having tensile strain, and a p-channel FET uses as a channel an SiGe layer having compressive strain. In order to form a CMOS circuit, it is necessary to form a Si layer having tensile strain and a SiGe layer having compressive strain on the same substrate.
With reference to FIGS. 1A to 1C, description will be made on a method of forming a Si layer having tensile strain and a SiGe layer having compressive strain on the same substrate (I. Aberg et al., IEDM Technical Digest, pp. 173 to 176, Dec. (2004)).
As shown in FIG. 1A, on a single crystal Si substrate 100 manufactured by the Czochralski method, a relaxation buffer layer 101 made of SiGe is grown at a growth temperature of 900° C. The relaxation buffer layer 101 has a higher Ge concentration with distance from the substrate 100, and a lattice constant at the upper surface of the relaxation buffer layer 101 is larger than that of Si.
Two etching stopper layers 102 and 104 made of SiGe and two strain Si layers 103 and 105 made of Si are alternately grown on the relaxation buffer layer 101 at a growth temperature of 680° C. The strain Si layers 103 and 105 have tensile strain because of lattice mismatch with the lattice constant at the upper surface of the relaxation buffer layer 101.
A strain SiGe layer 106 is grown on the strain Si layer 105 at a growth temperature of 525° C., and a strain Si layer 107 is grown on the strain SiGe layer 106. The strain SiGe layer 106 has compressive strain because of lattice mismatch generated by a lamination of the relaxation buffer layer 101 and strain Si layers 103 and 105. The strain Si layer 107 has tensile strain.
On the strain Si layer 107, a silicon oxide layer 108 is formed by low pressure chemical vapor deposition (LPCVD). Thereafter, annealing is performed at temperatures 650° and 750° to densify semiconductor material constituting each layer. After annealing, the surface of the silicon oxide layer 108 is polished to planarize the surface.
As shown in FIG. 1B, the silicon oxide layer 108 faces a handle wafer 110 to adhere to the handle wafer 110. As shown in FIG. 1C, layers from the Si substrate 100 to etching stopper layer 104 are removed by mechanical polishing or wet etching. In this manner, a hetero junction structure can be formed which has three layers of the strain Si layer 107, strain SiGe layer 106 and strain Si layer 105.
With the conventional method illustrated in FIGS. 1A to 1C, a lattice constant on the upper surface of the relaxation buffer layer 101 is less likely to be uniform in-plane, and is likely to be irregular. The lattice constant is changed in a thickness direction by intentionally generating transition in the relaxation buffer layer 101. Therefore, the crystal quality of each layer formed on and over the relaxation buffer layer is degraded. When this layer is used as a channel or the like of FET, reduction of a threshold voltage, increase of a leak current, etc occur. Manufacture processes are complicated, and special apparatus and chemicals are required which are not used by general semiconductor processes.